1. Field of the Invention
This invention relates to a data processing method and a data processing apparatus wherein AD (analog-digital) conversion is carried out and a solid-state image pickup apparatus, an image pickup apparatus and an electronic apparatus which are semiconductor apparatus for physical quantity distribution detection for which a mechanism for such AD conversion is utilized. More particularly, the present invention relates to a digital signal processing technique suitable for use with a semiconductor apparatus and other electronic apparatus for physical quantity distribution detection such as a solid-state image display apparatus wherein a plurality of unit components having sensitivity to electromagnetic waves inputted from the outside such as light or radiation are arrayed and a physical quantity distribution converted into an electric signal by the unit components can be read out as an electric signal through arbitrary selection by address control. More specifically, the present invention relates to a technique for acquiring digital data when a processing object signal is handled.
2. Description of the Related Art
In recent years, attention is paid to an image sensor of the MOS (Metal Oxide Semiconductor) type or the CMOS (Complementary Metal Oxide Semiconductor) type which can overcome various problems which a CCD (Charge Coupled Device) image sensor as a solid-state image pickup apparatus has.
For example, a CMOS image sensor includes an amplification circuit formed from a floating diffusion amplifier or the like for each pixel. Upon reading out of a pixel signal, as an example of address control, a method called column-parallel output type method or column type method is used frequently. In the method described, a certain row of pixels in a pixel array section is selected, and the pixels of the row are accessed simultaneously so that pixel signals are read out simultaneously and parallelly from the pixel array section with regard to all pixels of the row in a unit of a row.
Further, a solid-state image pickup apparatus sometimes uses a method wherein an analog pixel signal read out from a pixel array section is outputted after converted into digital data by an analog-digital conversion apparatus (AD conversion apparatus; Analog Digital Converter).
This similarly applies to an image sensor of the column-parallel output type, and various signal output circuits have been proposed. As one of the most advanced forms, a method has been proposed wherein an AD converter is provided for each column such that an image signal is extracted as digital data to the outside.
Meanwhile, various AD conversion methods have been proposed from the point of view of the circuit scale, processing speed (increase in speed), resolution and so forth. As an example, an AD conversion method called slope integration type or ramp signal comparison type (hereinafter referred to as reference signal comparison type) is available wherein an analog unit signal is compared with a ramp-shaped reference signal, that is, a ramp wave whose value varies gradually for converting an analog unit signal into digital data, and a counting process is carried out in parallel to the comparison process. Then, the digital data of the unit signal are acquired based on a count value at a point of time at which the comparison process ends. By combining the reference signal comparison type AD conversion method and the above described column parallel output type method, analog outputs of pixels can be AD converted column-parallelly in a low frequency band. Therefore, the combination is considered suitable for an image sensor which achieves both of high picture quality and a high speed.
Here, a pixel signal, particularly the difference between a pixel signal level of a pixel in a reset state and a pixel signal level when signal charge is read out, becomes a true signal component. Also where the reference signal comparison type AD conversion method and the column-parallel output type method are combined such that a pixel signal is converted into digital data simultaneously for all pixels of one row, a mechanism configured taking it into consideration that the differencing process is demanded is adopted. For example, a mechanism is sometimes adopted which carries out changeover of the counting mode between an up counting mode and a down counting is provided and changes over the counting mode depending upon AD conversion of the pixel signal level upon pixel resetting or upon AD conversion of the pixel signal level when signal charge is read out such that an AD conversion result of a true signal component is automatically acquired as a final AD conversion output value. In short, according to the mechanism described, a differentiating processing function is carries out simultaneously with AD conversion.
As a method of reducing power consumption of a counter circuit or an AD converter, for example, a method of providing a stopping period of counter operation, that is, a suspension period, is known and disclosed in Japanese Patent No. 3,338,294 (hereinafter referred to as Patent Document 1) or Japanese Patent No. 3,141,832 (hereinafter referred to as Patent Document 2). Another method of reducing the number of clocks or lowering the clock frequency is known and disclosed in Japanese Patent No. 3,507,800 (hereinafter referred to as Patent Document 3).
For example, Patent Document 1 discloses a method of reducing the power consumption of a counter circuit. More particularly, Patent Document 1 proposes a mechanism wherein, when a certain counter is operating, a counting operation of another counter is stopped and the number of times of reversing operation of a flip-flop is decreased to lower the power consumption.
Meanwhile, Patent Document 2 discloses a method which reduces the power consumption of an AD conversion apparatus. In particular, while a common counter circuit is used, AD conversion is carried out separately for higher order bits and lower order bits. As a method therefor, reference signals of different gains are compared with each other.
On the other hand, Patent Document 3 discloses a method of lowering the clock frequency for an AD conversion circuit. In particular, a reference signal of a stepped shape is used to carry out conversion operation separately for higher order bits and lower order bits. Reduction of the power consumption can be achieved by lowering the clock frequency.